文件名称:VERILOG_VERSION_PIC16C57
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VERILOG VERSION PIC16C57
是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
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下载文件列表
VERILOG VERSION PIC16C57
........................\Mini-Risc core _OPENCORES_ORG.mht
........................\picieee.tar.gz
........................\risc8.pdf
........................\synthpic.txt
........................\synthpic.zip
........................\Teaching IP core development- an example .pdf
........................\The Synthetic PIC.mht
........................\Mini-Risc core _OPENCORES_ORG.mht
........................\picieee.tar.gz
........................\risc8.pdf
........................\synthpic.txt
........................\synthpic.zip
........................\Teaching IP core development- an example .pdf
........................\The Synthetic PIC.mht