文件名称:dds_using_FPGA
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利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2,该环境集成了IP核,可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
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下载文件列表
dds_using_FPGA
..............\cos.mif
..............\cos_rom.bsf
..............\cos_rom.inc
..............\cos_rom.tdf
..............\db
..............\..\add_sub_6fg.tdf
..............\..\altsyncram_3u41.tdf
..............\..\altsyncram_4pi2.tdf
..............\..\altsyncram_90m1.tdf
..............\..\altsyncram_9pi2.tdf
..............\..\altsyncram_b431.tdf
..............\..\altsyncram_ut41.tdf
..............\..\altsyncram_vpl1.tdf
..............\..\dds.db_info
..............\..\dds.eco.cdb
..............\..\dds.sld_design_entry.sci
..............\..\decode_ogi.tdf
..............\..\mux_ogc.tdf
..............\dds.asm.rpt
..............\dds.done
..............\dds.fit.rpt
..............\dds.fit.smsg
..............\dds.fit.summary
..............\dds.flow.rpt
..............\dds.map.rpt
..............\dds.map.summary
..............\dds.pin
..............\dds.qpf
..............\dds.qsf
..............\dds.qws
..............\dds.tan.rpt
..............\dds.tan.summary
..............\dds_assignment_defaults.qdf
..............\dds_lut.bdf
..............\dds_lut.bsf
..............\dds_lut.v
..............\mux4.bsf
..............\mux4.inc
..............\mux4.tdf
..............\ram.bsf
..............\ram.inc
..............\ram.tdf
..............\sin.mif
..............\sin_rom.bsf
..............\sin_rom.inc
..............\sin_rom.tdf
..............\square.bsf
..............\square.inc
..............\square.tdf
..............\squra.mif
..............\cos.mif
..............\cos_rom.bsf
..............\cos_rom.inc
..............\cos_rom.tdf
..............\db
..............\..\add_sub_6fg.tdf
..............\..\altsyncram_3u41.tdf
..............\..\altsyncram_4pi2.tdf
..............\..\altsyncram_90m1.tdf
..............\..\altsyncram_9pi2.tdf
..............\..\altsyncram_b431.tdf
..............\..\altsyncram_ut41.tdf
..............\..\altsyncram_vpl1.tdf
..............\..\dds.db_info
..............\..\dds.eco.cdb
..............\..\dds.sld_design_entry.sci
..............\..\decode_ogi.tdf
..............\..\mux_ogc.tdf
..............\dds.asm.rpt
..............\dds.done
..............\dds.fit.rpt
..............\dds.fit.smsg
..............\dds.fit.summary
..............\dds.flow.rpt
..............\dds.map.rpt
..............\dds.map.summary
..............\dds.pin
..............\dds.qpf
..............\dds.qsf
..............\dds.qws
..............\dds.tan.rpt
..............\dds.tan.summary
..............\dds_assignment_defaults.qdf
..............\dds_lut.bdf
..............\dds_lut.bsf
..............\dds_lut.v
..............\mux4.bsf
..............\mux4.inc
..............\mux4.tdf
..............\ram.bsf
..............\ram.inc
..............\ram.tdf
..............\sin.mif
..............\sin_rom.bsf
..............\sin_rom.inc
..............\sin_rom.tdf
..............\square.bsf
..............\square.inc
..............\square.tdf
..............\squra.mif