资源列表
[VHDL编程] lab4_VHDL
说明:VHDL数字系统设计和工程实践2,包含原理,真值表和原理图,以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.<wangfeijum> 在 2024-05-20 上传 | 大小:23552 | 下载:0
[VHDL编程] lab5_VHDL
说明:VHDL数字系统设计和工程实践3,包含原理,真值表和原理图,以及VHDL源代码.-VHDL digital system design and engineering practice, 3, including the principles, truth table and schematic, as well as VHDL source code.<wangfeijum> 在 2024-05-20 上传 | 大小:6144 | 下载:0
[VHDL编程] lab6_VHDL
说明:VHDL数字系统设计和工程实践5,包含原理,真值表和原理图,以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.<wangfeijum> 在 2024-05-20 上传 | 大小:175104 | 下载:0
[VHDL编程] lab7_VHDL
说明:VHDL数字系统设计和工程实践6,包含原理,真值表和原理图,以及VHDL源代码.-VHDL digital system design and engineering practice, six, including the principles, truth table and schematic, as well as VHDL source code.<wangfeijum> 在 2024-05-20 上传 | 大小:75776 | 下载:0
[VHDL编程] Decoder
说明:This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder<hungnguyen> 在 2024-05-20 上传 | 大小:100352 | 下载:0
[VHDL编程] outshiftreg
说明:本代码实现了输出移位寄存器功能,初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn<tom> 在 2024-05-20 上传 | 大小:1024 | 下载:0