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PCI_target
- VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
CALCULAT.ZIP
- verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
KPCSMII
- Xillinx 的8位MCU软核的源代码，可在VertexII上运行，对CPU设计人员有很*意义-Xillinx the eight MCU soft-core source code can be run in VertexII. CPU designers to have great reference value
xc2s200pin_out_test
- 用于xillinx芯片xc2s200-pq208 PCI引脚测试的，有时担心焊接是否良好，需要测试PCI引脚，也可以修改后测试其它XILLINX芯片，对于想学习CPLD，FPGA的朋友有很大的帮助，可以学习引脚的绑定等等。
PCI_target
- VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
CALCULAT.ZIP
- verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
KPCSMII
- Xillinx 的8位MCU软核的源代码，可在VertexII上运行，对CPU设计人员有很*意义-Xillinx the eight MCU soft-core source code can be run in VertexII. CPU designers to have great reference value
xc2s200pin_out_test
- 用于xillinx芯片xc2s200-pq208 PCI引脚测试的，有时担心焊接是否良好，需要测试PCI引脚，也可以修改后测试其它XILLINX芯片，对于想学习CPLD，FPGA的朋友有很大的帮助，可以学习引脚的绑定等等。-Xillinx chip for xc2s200-pq208 PCI pin test, and sometimes worry that welding is good, need to test PCI pin
Ring_mem_VHDL
- 响铃和内存管理功能的VHDL语言，用于程控交换机中的Xillinx芯片与DSP和ADDA等芯片配合实现交换机的功能-Ringing and memory management features VHDL language, for program-controlled switchboards in Xillinx and ADDA chip and DSP chip, etc. with the function of switche
23-10111
- a simple serial to parallel converter using XILLINX and VHDL (the number of the project represents the binary code used by the converter e.g 23- 10111)
Counter_VhdlCode
- it is a simple counter written in vhdl , can be simulated using model sim worked on xillinx for fpga.
DDR2_hardcore_userguide
- xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
ttraafficLighr
- <p>交通灯状态机的实现，用verilog HDL编程与开发，Xillinx ISE 6仿真，在实际电路中的到验证． 已通过测试。</p> -<p> The implementation of the traffic light state machine, using verilog HDL programming and development, Xillinx ISE 6 simulatio
keypad_1
- keypad control system xillinx ise verilog
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
SyncounterFinal
- 在Xillinx ISE 平台上利用VHDL语言实现同步计数器，利用状态机实现，导入FPGA版点亮7段数码管并实现加、减计数功能。-The programme realizes a counter based on synchronous state machines, and it can be download to a FPGA chip.
dec38
- 在XIllinx ISE平台上利用VHDL基于结构化语句实现了38译码器。-The programme realizes an 3-8 decoder based on component descr iption through VHDL on Xillinx ISE.
wrpc-v2.0_src.tar
- About 1588 PTP protocol xillinx FPGA running code and Software application, and to introduce documents, want to help everyone
PCIe Solutions on Xilinx FPGAs 初学者指南
- PCIE在国内公布的xilinx入门文档，有效帮助初学者入门。(PCIE's Xilinx introductory document, which is published in China, helps beginners get started effectively.)
AXI4学习
- 关于XILLINX的AXI4总线协议的学习(Learning about XILLINX AXI4 Bus Protocol)