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Xilinx-modelsim-library
- Xilinx的modelsim 仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
vlog-spi
- 基于spi协议的串口实现， 用 ｖｌｏｇ编写．开发环境是modulesim！-agreement on the serial port, with vlog prepared. The development environment is modulesim!
CU.v
- 用vlog语言编写的cpu控制器源代码，用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
alu_vlog
- 学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
Xilinx-modelsim-library
- Xilinx的modelsim 仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
vlog-spi
- 基于spi协议的串口实现， 用 ｖｌｏｇ编写．开发环境是modulesim！-agreement on the serial port, with vlog prepared. The development environment is modulesim!
Vlog
- Write log in shell scr ipt
vlog.tar
- Linux 下vlogger*，可记录本地终端和远程会话-vlogger
vlog-tutorial
- Verilog Tutorial seminar-Verilog Tutorial seminar...
ModelsimVerilogWatch
- Stopwatch Design - ModelSim Vlog Tutorial Required Software: - Model Technology Modelsim 5.4a - Xilinx Development System 3.1i CONTROLS Inputs: * CLK -System clock for the Watch design. * STRTSTOP -S
dilbalu_fir1
- fir coding in vlog in fpga
8051vlog
- 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
log_severity
- DFATAL is FATAL in debug mode, ERROR in normal mode.Some flags needed for VLOG and RAW_VLOG.
vlogempire
- 风格模仿了世界著名Vlog网站Rocketboom的风格，并在其基础上作了美化 v2.0更新： 1.后台代码完全重写,模块划分更为清晰,程序更加安全可靠 2.全面支持目前主流视频格式,包括: mov,wmv,mpg,avi,rm,swf 等 (暂不支持flv格式) 3.优化所有页面的html代码，速度更快。 4.取消“作品名称”和“作品简介”的字数限制,首页文字以隐藏边框的text形式输出。 5.采用自定义分
vlogempire
- 风格模仿了世界著名Vlog网站Rocketboom的风格，并在其基础上作了美化-Blog imitate the style of the world famous site Rocketboom style and landscaping made on its basis