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gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occ
Ch6_Floorplanner
- xilinx virtex floorprint
gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occ
V4_FX_Mini_Module
- xilinx的嵌入式开发xps，virtex-4的mini开发板手册-Xilinx Embedded Development xps, Virtex-4 mini manual development board
V4ML401usersguide
- xilinx的嵌入式开发xps，virtex-4的401开发板用户手册-Xilinx Embedded Development xps, Virtex-4 401 development board user manual
Virtex-5family
- Virtex™ -5 系列提供 FPGA 市场中最新最强大的功能。Virtex-5 系列采用第二代 ASMBL™ （高级硅片组合模块）列式架构， 包含四种截然不同的平台（子系列），比此前任何 FPGA 系列提供的选择范围都大。每种平台都包含不同的功能配比，以满 足诸多高级逻辑设计的需求。-Virtex ™ -5 family provides the latest FPGA market, the most
FPGA_DSP
- Virtex-II Pro _ Virtex-II Pro X 完整数据手册(包含全部4个模块)；XtremeDSP开发套件Pro用户指南；及如何利用ML300 Virtex-II Pro开发系统着手开始搭建系统。-Virtex-II Pro _ Virtex-II Pro X Full Data Sheet (includes all four modules) XtremeDSP Development Kit Pro User
Final
- This module contains a digital clock which can enables clock setup option and up to four alarms. This was targeted Virtex-5 FPGA (ML501) and interfaced with LCD display. and center, north and east push buttons.
AdcData
- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcDataMultiChnl -- Purpose: Four channel version of the data capturing for a Texas Instruments ADC -- Tools: ISE, XST -- Limitations: none -- -- Re