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8051core-Verilog
- 利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！
8051core-Verilog
- 利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware descr iption language of the people to see!
miaobiao
- 完整的的倒计时秒表设计（指示带闪烁）ＶＨＤＬ代码，Ｑuartus 2开发环境，Archive文件，在Ｑuartus2解压即可。-Complete countdown stopwatch design (with flashing instructions) VHDL code, Quartus 2 development environment, Archive documents, in Quartus2 can extract.
gen_tb
- 用于verlilog自动产生testbench的脚本 用法：gen_tb <yourfilename>-Testbench for verlilog automatically generated scr ipt usage: gen_tb <yourfilename>
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
RS_decode
- RS（204,188）译码，verlilog硬件描述语言的实现-rs decode
FIFO Design Using Verlilog
- DFF with fifo concepts
verilog uart v1.0
- 基于Verilog语言写的UART模块，非常实用，可以参考，希望共同进步(Based on the Verilog language to write the UART module, very practical, you can refer to, hope to make progress together)