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digital_clock
- 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习
DDS
- DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法
digital_clock
- 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习-Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed an
PWM
- Core_PWM,verilog语言编写，可用于电机驱动-Core_PWM, verilog language, can be used for motor drive
DDS
- DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
VerilogHDL
- Veriolg HDL application for digital design
ethernet
- 以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
FFT_128_floating_point
- 基于Altera FPGA 的FFT128浮点运算模块(veriolg HDL+C51) (开发环境：KeilC51+Quartus7.2）-The module of 128 floating-point FFT based on Altera FPGA(veriolg HDL+C51) （Development environment：KeilC51+Quartus7.2）
verilog_exsample
- verilog入门学习代码，保证让你一看就会用VERIOLG-Introduction to learning verilog code, ensure that you will use VERIOLG a look
uart
- 用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。-a veriog program completed on FPGA to contrlo a uart to communicaton with a computer
labpgms
- Here are some of FPGA Based Veriolg Cose . Hope u all find it very useful in ur day activities enjoy
digital_clock
- 用Veriolg编写的数字钟实验，能进行时、分、秒计时的二十四小时制的数字钟，并具有定时与闹钟功能。-Digital clock with Veriolg written test, can be hours, minutes, seconds, the system timing clock digital clock and alarm clock with timing and function.
1_090303100007
- verilog tech for introducting the veriolg language, just for studying, not used for other occasion, thx for using this sample
sdh_pointer_deal
- 文件描述的是SDH 指针处理和系统同步代码 veriolg-SDH pointer processing and system synchronization code veriolg of file Descr iption
frequency_generator
- frequency generator veriolg code
key_debuouce
- veriolg 按键消抖的程序,可以写成模块，后面直接调用-verilog key debounce
LCD1602
- 这是veriolg版本的1602程序，写得很具体，还有必要的说明。用这个可以改成自由显示的那种。-This is a version of the 1602 verilog program, written very specifically, there is the necessary instructions. With this kind of freedom can be changed to display.
dds6_ise12migration
- 以DE2为开发平台，采用Veriolg语言编程，实现了DDS信号输出，频率，步进，波形输出均可调，采用Modelsim以及FPGA内嵌逻辑分析仪验证设计的正确性，可以满足一定的工程需求。(With DE2 as the development platform and Veriolg language programming, the DDS signal output, frequency, step and waveform out
spi_master
- spi通信主从模式 可以设置速率/工作模式(Master slave mode of SPI communication)
RSIC
- 包含控制部分和逻辑运算部分的精简CPU，适合verilog的初学者(Ti's a CPU which contain the part of chontrol and Arithmetic logic,it's approximate for people who contact veriolg with short time)