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基于半加器的全加器描述及仿真
- vhdl基于半加器的全加器描述及仿真-VHDL-based increases for the entire increase Descr iption and Simulation
verilog实例
- 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.
用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
add
- verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值-Adder Verilog generated the first 0-based values and binary values of the first value and a binary-based values of the first two binary-based value and the value of
adder4
- verilog加法器,附加测试文件 可用modelsim 仿真实现-Verilog Adder, additional test file ModelSim simulation can be used to achieve
VerilogHDL_StepperMotor_control
- 采用Verilog HDL语言编写的步进电机位置系统，实现步进电机的定速、加速、减速、定位，且速率和加减速度都能做到连续可调的程序，对控制类相关的学习者价值很高-Using Verilog HDL language of the stepper motor position system, stepper motor speed, acceleration, deceleration, positioning, and speed an
add_64
- 64位verilog加法器，希望对大家有帮助-Verilog 64-bit adder, and they hope to help everyone
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and m
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Verilog
- 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
64B_adder
- Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
verilog-example
- 4位并行乘法器 4位超前加法器 ALU 计数器 滤波器 全加器 序列检测器 移位器-failed to translate
verilog
- verilog verilog+十大基本功能 很实用，入门加提高，经验-verilog verilog+ ten basic functions very practical, entry-plus increase, experience
verilog
- 经典Verilog源代码，包括加法器，滤波器和qpsk的设计-Classic Verilog source code, including adders, filters and qpsk design, etc. ...
add32
- 32位加法器，verilog实现，且有仿真图像-32-bit adder and programed by veilog
add
- verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)
常用加法器设计
- 采用Verilog设计的几种常用加法器。(several adder designed by Verilog)
超前进位加法器
- 8*8超前进位加法器，Verilog初学教程(file name is adder.v adder 8*8 bit)
4Bit超前进位加法器门级电路设计与仿真
- 用门级网表的方法对4Bit超前进位加法器门级电路连接关系用verilog语言进行描述(The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist)