搜索资源列表
串口通信收发模块
- verilog编写的串口通信的接收模块和发送模块，经过仿真有效
RS232
- FPGA实现RS-232串口收发的Verilog程序，已经调通。-FPGA realization of RS-232 serial port to send and receive the Verilog procedures, Qualcomm has been transferred.
FPGA
- 用verilog实现的串口收发数据程序，已经调试通过-Using Verilog to send and receive data to achieve the serial procedures are debugging through
FPGA-URAT
- FPGA与PC串口自动收发程序,verilog源程序-FPGA and the PC serial port automatically sending and receiving process, verilog source code
my_232
- verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Verilog-uart
- Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
uart_verilog
- 一个VERILOG串口收发的例子，可以收发单字节，适当加小量代码就可实现任意字节的接收。-VERILOG a serial port to receive example, can receive a single byte, appropriate to add a small amount of code can be any byte receive.
FPGA-rs232(verilog)-2
- FPGA rs232串口收发程序，3个程序任意选择，全部可用-FPGA rs232 serial transceiver procedures, three procedures arbitrarily selected, all available
基于FPGA的串口通信系统
- 该设计是基于 FPGA 的串口通信系统模拟仿真，通过对 RS-232 串行总线 接口的设计，掌握发送与接收电路的基本思路，并进行串口通信。采用 Verilog HDL 语言对 UART 波特率产生模块、数据发送模块、接收模块进行硬件描述， 再将其整合为一个 RS-232 收发模块，最终在顶层模块中将两个 RS-232 模块例 化，实现两块 FPGA 芯片全双工通信的设计。(Design of serial communication s
LAB9_UART
- Verilog串口收发的程序及说明。。。。。。(Verilog rx_uart r_uart x_uart)
uart
- 一个具有固定波特率的 UART 串口收发器，可以实现 串口收发器，可以实现 9600 波特率的串口通信， 能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication
verilog串口通信程序
- 串口通信程序，用于fpga的串口收发，并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)
uart
- 串口发送接收模块，verilog语言，可用来做hdl设计的仿真(used for test for Uart interface in FPGA)
uart_fifo_n
- verilog 带fifo的串口收发模块(verilog uart with fifo)
FPAG UART Verilog
- FPGA实现URAT，实现异步串口收发控制(FPGA implements URAT to realize asynchronous serial port and transceiver control)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and recei
uart
- 实现串口的收发，可以稳定的运行，经过测试，可以完全应用于项目中。(The implementation of the serial port and transceiver, can run stable)
基于FPGA与PC串口自收发通信-Verilog
- 基于FPGA与PC串口自收发通信-Verilog(Self-transceiving Communication Based on FPGA and PC Serial Port-Verilog)