搜索资源列表
串口verilog源代码
- 串口UARTverilog源代码。包括控制模块、收、发模块。程序全，功能简洁，包含Q2工程
uartverilog
- 8251的verilog 代码
uart_51
- 符合8051协议规范的UART的Verilog源代码.该压缩包是一个modelsim的工程.-8051 agreement in line with the norms of the Verilog source code UART. The Compression Pack is a ModelSim project.
uartverilog
- xilinx提供的verilog_uart源码,适合做串口的人学习-Xilinx provided verilog_uart source, suitable for those who study serial
uartverilog
- 实现cpld和pc机之间的串口通信，PC机传送到CPLD的信息，CPLD传回到PC机-Via verilog language ，cpld can communcate with pc.
UARTverilog
- 用verilog语言实现的UART内核，可以直接拿来用。-it is writen by verilog，it is uart，it can use directly
17869318fpga-example1
- FPGA实例包含UARTverilog TLC7524接口电路程序 TLC5510 VHDL控制程序 DAC0832 接口电路程序 LCD控制VHDL程序与仿真等-FPGA interface circuit examples include UARTverilog TLC7524 TLC5510 VHDL process control procedures procedures DAC0832 LCD control interfa
uartverilog
- Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
uartverilog
- 该程序用VerilogHDL编写，主要用CPLD的EPM240T100C实现了RS-232的通信，供大家参考-VerilogHDL written by the program, mainly realized by CPLD' s EPM240T100C RS-232 communications for your reference
uartverilog
- 这是基于BJ-EPM240学习开发板的串口通信实验程序-This study is based on BJ-EPM240 development board serial communication experiment program
uartverilog
- 用verilog语言编写uart程序。模拟串口时序进行收发数据操作。-verilog uart
uartverilog
- RS232接口，有接收器和发送器和分频器，有详细说明-RS232 interface, a receiver and transmitter and the divider, a detailed descr iption
uartverilog
- verilog hdl FPGA vga时序显示经典源程序 很实用的-verilog hdl FPGA vga display timing source code very useful
uartverilog
- 该程序是Verilog写的串口收发程序，具有基本的收发功能，经过验证，能使初学者很好了解rs232，和Verilog-The program is written in Verilog serial transceiver program, with the basic send and receive functions, proven, good for beginners can understand rs232, and Ver
uartverilog
- 有关于CPLD的例程。芯片为MAXII，在quartusII下开发，是一个串口例程。-On CPLD routine. The chip is MAXII, in quartusII under development, is a serial routines.
uartverilog
- 本程序是基于verilog HDL的串口程序，需要的下载-This procedure is based on Verilog HDL serial procedures, the need to download
uartverilog
- FPGA与上位机通过串口调试助手进行串口通信，回发传过来的数据-FPGA and host computer through the serial port debugging assistant serial communication, and pass over the data postback
uartverilog
- 串口收发程序verilog版本，适用于ALTERA的CPLD-Serial transceiver Verilog version, applicable in ALTERA CPLD
uartverilog
- 串口的FPGA工程，经过测试，绝对可用。-Serial port of the FPGA project, tested, and absolutely available.
uartverilog
- 基于fpga的verilog写的uart串口通信实验-Based fpga the verilog write uart serial communication experiment