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unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY U
自动售货机VHDL程序与仿真
- library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_auto1 is port ( clk:in std_logic; --系统时钟 set,get,sel,finish: in std_l
unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY U
DEC_7SEG
- library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all
motor_control
- LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL
robot_ctl
- -- Simple Robot Control Program -------------------------------------------------------------------------- library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.al
servo_control
- library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all
HammingDecoder
- -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.co
FIFO_design_reference_document
- FIFO设计的参考文档 Project name : Fifo -- Project descr iption : Fifo controller Unit 工程名 : FIFO.VHD 用到库文件IEEE.STD_LOGIC_1164-FIFO reference design document Project name : Fifo -- Project descr ipti
keyboard_vhdl
- ps2 keyboard with encoding ascii code to 7-segments screeen. LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY klawa IS PORT ( keyboard_cl
sy3
- 多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all
sy2
- 晶振频率为4.096MHz，系统同步时钟为256KHz，每个时隙占8位； 四路支路信码各为8位，分别为： 1 1 1 0 0 1 0 1 ；1 1 0 1 1 0 0 1 ；1 0 0 1 1 1 0 1 ； 1 1 1 0 1 0 1 1 ； 复接方式采用：按位同步复接。 -library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsig
hdb3
- hdb3编码源程序完整版，内含插B，插V程序，功能完整，欢迎下载-library ieee use ieee.std_logic_1164.all entity hdb3 is port(codein: in std_logic clk : in std_logic clr : in std_logic --复位信号
std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic
VHDLSaler
- 文件名：pl_auto1.vhd。 --功能：货物信息存储，进程控制，硬币处理，余额计算，显示等功能。 --说明：显示的钱数coin的 以5角为单位。-library ieee use ieee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port
Cvolatile
- eee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic --系统时钟 set,get,sel,finish: in std_logic --设定、买、选择、完成信号 coin0,coin1: in std_l
clock
- eee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic --系统时钟 set,get,sel,finish: in std_logic --设定、买、选择、完成信号 coin0,coin1: in std_l
vhdl
- 4位乘法器 vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port ( A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC ) en
std_logic_1164
- std_logic_1164 package