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ssram.tar
- implemention of ssran in VHDL
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be r
256X8 SSRAM 建模仿真与综合
- 一篇关于ssram建模仿真的文献
sram_verilog
- 告诉图形采集 verilog代码 很简单的 第一次发-tell graphics Acquisition Verilog code is very simple first grant
ssram.tar
- implemention of ssran in VHDL
GetprocessRam
- 该程序可以获取任意运行进程的内存使用信息以及页面文件使用，程序中包括一些加载窗体，创建数组测试。-the program can get the process running the arbitrary use of information and memory page document use, procedures include some loading windows, creating an array testing.
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be r
altera_avalon_cy7c1380_ssram
- 关于altera的SRAM的读写控制IP代码，有兴趣的朋友可以下去-On the SRAM
DE1_SD_Card_Audio
- SD卡操作模块，一个简单的sd卡使用实例-SD card operation module, a simple example of the use of sd cards
SSRAMcontroller
- SSRAM控制器,vhdl实现并通过验证-ssram controller,implement by vhdl and complier
Memory
- 存储器类型介绍:SSRAM SDRAM Flash Memory EEPROM EPROM-Memory Introduction
AHB_SRRAM
- SSRAM with AHB bus interface source code
ssramWR
- SSRAM CY7C1383C的读写延时控制程序-CY7C1383C delay control procedures to read and write
mem_ctrl
- 老外写的通用的存储器控制核，支持SDRAM SSRAM FLASH,ROM等等 8个片选信号 支持RMW cycles最大可达9*64M Bytes的存储器容量-Written by foreigners universal memory controller core, support for SDRAM SSRAM FLASH, ROM, etc. 8 chip select signals support RMW cycles u
vga_gui
- 在DE2开发板上实现，由于DE2中的SSRAM只有512K，所以640*480*3（byte）的显存是不够的显示结果是经缩放 后的效果，具体可修改Altera_UP_Avalon_Pixel_Buffer buffer模块中的相关代码。 我把代码移植到DE2-70上后，显示的就很正常了。-In the DE2 development board to achieve, due to the SSRAM DE2 onl
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
71V25761_Verilog_99056.tar
- SSRAM Simulation Model
ssram-and-tesebench
- 实现一个256x8的同步静态存储器SSRAM，用硬件描述语言Verilog写的，同时谢了测试程序-it realized a 256x8 SSRAM,writen by Hardware descr iption language Verilog ,and include the testbench.
ssram
- ssram using VHDL code
SSRAM-to-NOR-Flash-Bridge
- nor flash（m29w128g）的读，写，擦出等操作，另一边是标准的SSRAM操作接口。--one port is nor flash interface，including the basic operation of nor flash（m29w128g）；the other one is standard ssram interface。