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- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
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- 数字秒表的整个设计以及程序．波形仿真都在里面的了
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- 数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
shuzimiaobiao
- 数字秒表的整个设计以及程序．波形仿真都在里面的了-Digital stopwatch, as well as the entire design process. Waveform simulation are inside the
shuzimiaobiao
- 数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through th
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- 秒表的逻辑结构比较简单，它主要由、显示译码器、分频器、十进制计数器、报警器和六进制计数器组成。在整个秒表中最关键是如何获得一个精确的100Hz计时脉冲，除此之外，整个秒表还需要一个启动信号和一个归零信号，以便能够随时启动及停止。 秒表有六个输出显示，分别为百分之一秒，十分之一秒、秒、十秒、分、十分，所以共有6个计数器与之对应，6个个计数器全为BCD码输出，这样便于同时显示译码器的连接。当计时达60分钟后，蜂鸣器鸣响10声。 -
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- 数字秒表程序，能从0到99计数，按键启动，使用AT89S51,使用汇编语言编写，易于初学者参考-Digital stopwatch program, from 0-99 counting, start button, use the AT89S51, the use of assembly language to prepare, easy for beginners reference
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- 89s52实物测试通过,四位数码管动态显示分钟和秒表,c51编程,带有详细注释,适合初学者学习.-89s52-kind test, and four digital control dynamic display minutes and stopwatch, c51 programming, with detailed notes, suitable for beginners to learn.
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- 这是微机原理课程设计的实验报告，包含接线图，源码等，希望对大家有所帮助-This is the principle of curriculum design, computer experimental report, including wiring diagrams, source code and so on, want to help everyone
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- 题目 电子秒表模拟程序设计 一、设计目的：掌握定时/计数器8253和中断的使用。 二、设计任务：编写汇编程序，在PC机上完成电子秒表功能。 -Subject of electronic stopwatch simulator designed, designed to: master the timer/counter 8253 and interrupted use. Second, the design task: th
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- 51单片机 数字秒表的proteus仿真，两位数码管显示-51 MCU digital stopwatch proteus simulation, two digital display
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- 秒表设计中的分块模块的设计，运用VHDL语言编写-Stopwatch design block module design, the use of VHDL language
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- 数字秒表，要求从00:00秒开始计时，最大计时时间为99:99秒。并且具有启动、暂停和清零（复位）等功能。-Digital stopwatch, requiring from 00:00 seconds to start the timer, the maximum time of 99:99 seconds time. And has a start, pause, and clear (reset) and other functi
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- 秒表程序课程设计，可以让那些不想写设计报告的人直接使用-stopwatch curriculum design process, allowing those who do not want to write the design report directly use
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- FPGA开发实例 之 数字秒表.七段码管显示.秒表由于其计时精确，分辨率高（0.01秒），在各种竞技场所得到了广泛的应用。-FPGA development instance of digital stopwatch. 7 yards tube display. Stopwatch because its timing precision, high resolution (0.01 seconds), the income to th