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DCT
- 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过
DCT
- 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
systemTray.tar
- JAVA SE6.0 桌面编程实现 System tray 图标-JAVA SE6.0 Desktop Programming System tray icon
jse6_student_materials
- JAVA source code with book JAVA SE6
examples
- 这个是JAVA SE6的程序范例 大家可以下载看看！-JAVA SE6 This is an example of the process you can download to see!
java2-learning
- JAVA+SE6全方位学习源代码 台湾朱仲杰编著-JAVA+SE6 course/java/program/
ModelSim_SE_6.5_downloads_install_Configuration.ra
- 详细的介绍了modelsim的下载，破解，编译xilinx库，配置的问题，非常详细-Described in detail modelsim download, crack, the compiler library xilinx, configuration problems, in great detail
Java-JDK-5.0studynote
- 《Java JDK6学习笔记》是作者良葛格本人近几年来学习Java的心得笔记，结构按照作者的学习脉络依次展开，从什么是Java、如何配置Java开发环境、基本的Java语法到程序流程控制、管理类文件、异常处理、枚举类型、泛型、J2SE中标准的API等均进行了详细介绍。本书还安排了一个“文字编辑器”的专题制作。此外，Java SE6的新功能，对Java lang等套件的功能加强，以及JDBC4.0、Apache Derby纯Java数据库
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
div_n_0_5
- 使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
SCJP-Study_Guide_2009
- SCJP: Sun Certifi ed Programmer for Java Platform, SE6 Study Guide. This book is part of a family of premium-quality Sybex books, all of which are written by outstanding authors who combine practical experience with
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is
SL-275-SE6
- This pdf is about "Introduction to java"
test_pll
- 使用modelsim se6.5d仿真altpll锁相环 完整工程，verilog代码，因为没找到选的是vhdl-simulation pll with modelsim se6.5d
SCJP
- SCJP Sun Certified Programmer for Java® Platform, SE6 Study Guide-SCJP Sun Certified Programmer for Java® Platform, SE6 Study Guide
fir_lowpass
- 硬件语言实现数字低通滤波器，使用ise11.1和modelsim se6.5 仿真测试-Hardware language digital low pass filter, the use of simulation testing ise11.1 and modelsim se6.5
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
DCT
- 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
handshack
- 握手机制的仿真，用ISE14.7打开，modelsim se6.5(Hold the simulation of mobile phone system, open with ISE14.7, Modelsim se6.5.)