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Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996
Verilog_HDL-SamirPalnitkar
- This book is for verilog HDL by Samir Palnitkar.
AODV-code
- 它是反应式路由协议，也就是说当向目的节点发送包时，源节点才在网络中发起路由查找过程，找到相应的路由。相反的，很多普通的因特网路由协议都是先验式的，也就是说它们查找路由是不依赖于路径上的节点是否要发包，而是每个节点维护一张包含到达其它节点的路由信息的路由表。节点间通过周期性的交换路由信息来不断更新自身的路由表，以便能够及时的反映网络拓扑结构和变化，以维护一致的、及时的、准确的路由信息。正如协议的名字所示，无线自组网按需平面距离矢量路由协议
1904.Verilog-HDL-by-Samir-Palnitkar
- VLSI book for vhdl and verilogg HDL coding
aodv_v8
- The AODV code developed by the CMU/MONARCH group was optimized * and tuned by Samir Das and Mahesh Marina, University of Cincinnati
davidscherer-glowscript-c1d642e5b217
- magnetic field strength, making this approach unsuitable for deep space missions, and also more suitable for low Earth orbits as opposed to higher ones like the geosynchronous. The dependence on the highly variable
samir
- Application of genetic algorithms to solve NP is considered an effective means of problem solving to optimize logistics and distribution vehicle routing problem, in the traditional genetic algorithm based on immune algor
VerilogHDL
- Samir Palnitkar-Verilog HDL_ a guide to digital design and synthesis-SunSoft Press (2003)
Palnitkar_Verilog_1996
- Samir Palnitkar-Verilog Digital Design Synthesis-SunSoft Press (1996)