搜索资源列表
or1200
- or1200的内核以及一些参考文献,是Verilog的RTL级描述。-or1200 core as well as some references, is the RTL-level Verilog descr iption.
8051_IP_Verilog
- 8051单片机源码verilog版本 包括rtl, testbench, synthesis -Verilog source code version of 8051, including rtl, testbench, synthesis
i2c.tar
- 是个I2C软核,使用verilog和vhdl实现的,含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
mem-ctrl-rtl
- 实现对ddr的控制,可以在fpga的仿真环境下跑程序,并有testbench可以参考-implement ddr control
src
- FIR滤波器的设计,完整包括RTL代码、testbench等,清晰易懂。-FIR filter design, complete coverage of RTL code, testbench, etc., clear and understandable.
Camera_Interface_Verilog
- 该源代码包是基于片上系统的摄像头接口的Verilog语言程序,它包括以下5部分:RTL源代码,测试平台,软件仿真C代码,FPGA综合时的sdc和ucf文件,说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, t
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型,包括以下4个部分:RTL源代码,测试平台,软件仿真代码,说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包,它包括以下4部分:RTL源代码,测试平台,软件仿真文件,说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, softw
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help document
ethernet_tri_mode_latest[1].tar
- ethernet_tri_mode from opencores.org inlcude rtl and testbench
fre
- verilog hdl 开发的频率计,运行环境 DE2-115开发板,内有modelsim仿真用的testbench。RTL级代码-verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code
matrix-keyboard-
- 矩阵键盘控制的FPGA,verilog语言实现,包括rtl,ucf,以及testbench的详尽代码-Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench
generic_fifos_latest.tar
- fifo的verilog代码,包含rtl,sim,testbench内容的verilog代码,完全可用-rtl code of a fifo
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Dist
syncram
- verilog rtl and testbench code for single port sync ram
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现,包含详细GPIO定义文档,testbench,RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
ddr_controller
- 完整的DDR控制器设计,包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)