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risc cpu
- 一个很好的16位cpu ip内核，用quartus写的
freerisc8_11
- 8位RISC CPU的VERILOG编程 SOURCECODE-8 RISC CPU VERILOG programs SOURCECODE
靳远－源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
ethernet_verilog
- 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu.
cpu的VERILOG描述
- RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL descr iption
embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
RISC
- hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
16_risc_cpu
- 一个支持精简指令的16位的risc cpu，可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
cpu
- 精简指令cpu，用verilog编写，详细的教程-RISC cpu, using Verilog prepared and detailed tutorial
RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
alu
- 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
ARelativelySimpleRISCCPU
- A Relatively Simple RISC CPU 设计源码并附详细的说明文档。可以ModelSim进行仿真，并可以用synplify进行综合。-A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.
RISC_CPU
- RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design m
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
RISC_8
- 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
risc
- 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design