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A New Phase-Locked Loop (PLL) System
- An enhanced phase-locked loop (PLL) system is presented and its properties and performance characteristics are investigated. Advantages of the proposed PLL structure over the conventional PLLs including its capability
pllset_rev121
- s3c2410 pll 计算程序-computational procedures s3c2410 pll
FM_phase_noise_
- The file calculates and plots FM noise sidebands for a carrier. It also does sinusoidal modulation. This simple way of adding noise to a carrier is useful for simulation of PLLs. It turns out, though, that the mean of th
PLLpostprocesser
- this the phase locked loops post processer.PLLs are widely used in frequency synthesis, for frequency multipliers and dividers, for carrier and symbol synchronization, and in the implementation of coherent receivers-this
FirstOrderDigialFiltersforSeond-OrderDigitalPLLs.
- This a short paper discussing three implementations of digital loop filters for phase-locked loops (PLLs) implemented either in digital circuitry or in software. This paper is by no means intended to be a comprehensi
8616039-PLL-Design-Part-2
- Phase-Locked Loops for High-Frequency Receivers and Transmitters–Part 2 by Mike Curtin and Paul O’Brien The first part of this series of articles introduced the basic concepts of phase-locked loops (PLLs). Th
FM_phase_noise_1
- The file calculates and plots FM noise sidebands for a carrier. It also does sinusoidal modulation. This simple way of adding noise to a carrier is useful for simulation of PLLs. It turns out, though, that the mean of th
dvb-pll-
- descr iptions + helper functions for simple dvb plls.
PLLs
- PLL: Phase-locked loop
dvb-pll
- descr iptions + helper functions for simple dvb plls for Linux.
mst717
- The MST717 is a highquality ASIC for NTSC / P AL car TV application. It receives analog NTSC / P AL CVBS and S-V ideo inputs from TV tuners, DVD or VCR sources, including weak and distorted signals, as well as analog
Clock_gen_altpll
- Generate clock using plls.
evergreen_cs
- Get the resulting clock rate a PLL register value and the input frequency. PLLs with this register layout can be found on i.MX1,. -Get the resulting clock rate a PLL register value and the input frequency. PLLs with t
trio_shm_def
- Berlin2 SoCs comprise up to two PLLs called AVPLL built upon a VCO with 8 channels each, channel 8 is the odd-one-out and does not provide mul div.
dvb-pll
- descr iptions + helper functions for simple dvb plls.
TSEK03_2017_T5_PLL
- Good source to design PLLs.