搜索资源列表
ref3
- nexys 2 vhdl reference project for uart
uart_vhd
- Test Uart on board Nexys 2by VHD
vacantfiles3
- nexys 2 vga working files
Lab01
- 快速熟悉ISE软件的使用，适合初学者，是一系列小操作流程的集合。-To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD circ
2FSK_decode
- 程序实现2FSK的解调，使用过零检测法，分为预处理模块和鉴频处理模块，Verilog语言，在modelsim仿真通过-2FSK Program for demodulation of zero-crossing detection method used, divided into pre-processing module and the discriminator processing module, Verilog languag
lab1
- xilinx官网edk实验，lab1，用nexys 2 板实验源代码-xilinx edk official website experiments, lab1, with nexys 2 plate test source code
lab2
- xilinx官网edk实验，lab2，用nexys 2 板实验源代码-xilinx edk official website experiments, lab2, with nexys 2 plate test source code
Nexys2_sch
- digilent最新fpga开发板nexys原理图资料，非常详细，规范。-digilent latest fpga development board nexys schematic information, very detailed, specification.
SGvga
- 基于System Generator 实现Xilinx FGPA的VGA显示模块，板块Nexys™ 3 Spartan-6 FPGA Board，可以直接把.bit文件下进去进行。 具体说明可以参考本人博客：http://www.openhw.org/wenlong0601/blog/12-03/239390_f7ef3.html-Based on the System Generator Xilinx FGPA VGA
dcmotor
- PID dc motor control on Nexys 2 FPGA
nexys-fingerprint-system
- 大学生体育管理系统 NEXYS3 指纹识别-NEXYS3 FINGERPRINT RECOGNITION
vhdl-clock-with-vga-output-for-Nexys-2
- Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vh
Alu-with-seven-segmetn-output
- This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for t
UART_VHDLsouce
- nexys 2 examples for improve study of vhdl digital design using diligent fpga board
Frecuenciometro
- Mide y muestra en una nexys la frequencia dada digitalmente en los displays
TP1_ALU
- Unité arithmetique et logique Nexys 2 board
7segment-display-VHDL
- 使用的NEXYS2原型设计电路板的7段编码器模拟-using the NEXYS 2 prototyping board Simulate the 7-segment encoder
mywork
- nexys 3 板卡，打砖块游戏。连上VGA接口，然后将mywork文件夹里的所有内容考到一个新建的文件夹下，不要有中文目录。下载运行就行了。-Nexys 3 board card, Arkanoid game. Connected to the the VGA interface, and then will mywork file folder li the all the contents of test to the a the
try_ram
- Verilog Codes for RAM-Testing. Write data in the RAM and read it out from the RAM. Tested on NEXYS 3.
facman
- 一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。-A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3