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verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
jishushizhong
- 用EDA开发板实现的24小时计数时钟，编程环境为MUXPLUS2.-EDA development board used to achieve the 24-hour count of the clock, programming environment for MUXPLUS2.
yueqvyanzou
- 基于MUXPLUS2的VHDL程序，实现音乐播放，-MUXPLUS2 the VHDL-based procedures, the realization of music player,
jisuanqi
- 用VHDL语言实现通用计算器设计，MUXPLUS2软件仿真验证-Implementation using VHDL language design generic calculator, MUXPLUS2 software simulation to verify
count999
- vhdl实现的计数器,可以从0记到999,该代码使用模块化设计思想,开发工具muxplus2-achieved vhdl counter, can be recorded from 0 to 999, the code uses the modular design concept, development tools muxplus2
SHIZI
- 汉字数字显示，用VHDL语言编写，开发环境为MUXPLUS2-HANZIXIANSHI
unit5
- 低频数字式相位测量仪 使用的VHDL语言，在MUXPLUS2环境下使用！ -digit hpase detecter use for low-frequence
MUXplus2
- Max+plusⅡ是Altera公司提供的FPGA/CPLD开发集成环境，Max+plusⅡ界面友好，使用便捷，被誉为业界最易用易学的EDA软件。本资源分七节内容详细的讲解了MUX+PLUSⅡ软件的操作及应用。-Altera Max+ plus Ⅱ is provided by FPGA/CPLD development integration environment, Max+ plus Ⅱ friendly interface an