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miniuart_vhdl
- 用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware descr iption language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
rs232
- this is a vhdl version of MiniUART implementation
miniuart
- vhdl实现miniUART代码 分模块设计和状态机设计,内核超级小
miniuart.tar
- miniuart 串口源码程序 VHDL语言
miniuart
- This is a uart source written by VHDL .widely used and compatible with Whibone.
rs232
- this is a vhdl version of MiniUART implementation
miniuart
- vhdl实现miniUART代码 分模块设计和状态机设计,内核超级小-VHDL code miniUART to achieve sub-module design and state machine design, super small kernel
miniuart.tar
- miniuart 串口源码程序 VHDL语言-miniuart serial VHDL language source program
miniuart
- This is a uart source written by VHDL .widely used and compatible with Whibone.-err
miniUART
- 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
miniUart
- 一个简单的uart的VHDL描述，希望对大家有点帮助-A simple UART in VHDL descr iption, I hope all of you a little help
miniuart.tar
- Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication
miniuart.tar
- 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL descr iption with a simple UART interface
system05_latest.tar
- 6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz
miniuart-1.0.0.tar
- wishbone uart controller