搜索资源列表
SF2_USB_tutorial
- Microsemi SmartFusion2 USB实验教程，包括FPGA和M3两部分程序-Microsemi SmartFusion2 USB experimental curricula, including the two-part program FPGA and M3
VerilogUart
- UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
CoreUartTest
- Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 har
m2s050-som-fg484-1a
- Microsemi M2SSOM KIT Project
microsemi
- microsemi的Libero IDE 软件内部IP核详解(Microsemi's Libero IDE software internal IP kernel details)
test56_PWM3
- VHDL 3 phase of PWM microsemi project
test59_TRIGU
- VHDL generating of trig signal microsemi project
test60_TRIGD
- VHDL generating of trig down signal microsemi project
test51_PLL
- VHDL How to use PLL-IP core microsemi project
test42_CoreABC
- VHDL How to use CoreABC-IP with uart microsemi project
sf2_igl2_ds_v1
- Microsemi IGLOO2系列FPGA器件的数据手册，很全面。(Microsemi FPGA datasheet.)
pfsoc_mss_sim_ug
- The PolarFire SoC FPGA's Microcontroller Subsystem (MSS) is modeled with Microsemi's AMBA Bus Functional Model (BFM) and it is limited at FIC itself. For information about the supported instructions and syntax of the B