搜索资源列表
ISE12.4 lic
- ISE 12.4 license文件
ipcore
- XILINX公司ISE自带的IP核，功能介绍，如何使用这些IP核来加快你的开发。-IP release note guide
mgc_licen(1)
- license for ise12.2,最新而且很好用，请放心使用。-license for ise12.2，It s lastest fot ise 12.2,good ease to ues.
XilinxISEDesignSuite12.3Tutorial
- 最新Xilinx ISE12.3 开发环境使用指南-The Guide of the latest Development environment for Xilinx ISE12.3
xilinx_ise_12
- 最新xilinx_ISE-12.3 version License 扩展名.lic-xilinx_ISE-12.3 version License
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
PWM_extend
- 本代码采用RTL级的硬件描述语言设计了一个多通道的PWM波形捕获、输出模块。主要用在无人机或是其它需要控制多个伺候电机的场合。开发环境为Xilinx公司的ISE12.0。-This code uses RTL-level hardware descr iption language designed a multi-channel PWM waveform capture, output module. Mainly used in t
UARTModule
- Uart的VHDL实现，用ISE12.1建的项目。-Uart usingVHDL to implement
IICComponent
- IIC的vhdl实现，用ISE12.1建的项目，读取eeprom的接口代码-using FPGA to communicate with the EEPROM through IIC connector
ISE-12.3-Guide
- 本文为ise12.3详细开发步骤，对新手会非常有帮助的。-This article ise12.3 detailed development steps, the novice will be very helpful.
uCOS_xilinx-FPGA
- uCOS在xilinx FPGA上的移植代码和BSP编写工程，配合ise12.3使用。-uCOS transplant in xilinx FPGA code and BSP on writing projects, with ise12.3 use.
modelsim
- 讨论在ModeSim_SE中指定ISE12[1].x的仿真库-modelsim simulation discuss
Channel_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
IFFT11111
- 使用Verilog编写的IFFT，ISE12.2下编译通过，学习IFFT核的同学可以参考-Use of the IFFT in Verilog compiler, ISE12.2 under study IFFT core students can refer to
Phase1111_Tracking
- 使用Verilog编写的相位跟踪器，可以有效解决锁相环中的相位跟踪问题，ISE12.2下编译通过-Written in Verilog phase tracker can effectively resolve the PLL phase tracking, ISE12.2 compiled by
Timing1111_Symcronization
- 使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过-Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by
Viterbi11111
- 使用Verilog编写的vertbi译码模块，ISE12.2下编译通过，主用是调用ISE下的Vertibi核设计实现的。-Written using Verilog vertbi decoding module, ISE12.2 compiled by the main use is to call ISE the nuclear Vertibi designed to achieve.
FPGA_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
CarrierNco
- ISE12.3环境下编写的载波NCO的产生程序，进行扩频通信或者卫星导航研究的同学可以参考-ISE12.3 environment prepared by the carrier NCO generator, spread spectrum communication or satellite navigation research students can refer
Xilinx-Downloader
- 这是一个Xilinx并口下载线的图纸，可下载Xilinx的CPLD\FPGA,本人试制成功过，并在ISE12.1下载验证。-This is the drawing of a Xilinx parallel port download cable, downloadable Xilinx CPLD \ FPGA, I succeeded in the trial, and in ISE12.1 Download verification.