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fpga时钟设计
- 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操 作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将 导致错误的行为，并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可 分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上 述四种时钟类型的任意组合。-without the expense of
9.4_PULSE_FRE
- 基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 9.4.1 脉冲频率的测量原理 9.4.2 频率计的工作原理 9.4.3 频率测量模块的设计与实现 9.4.4 while循环语句的使用方法 9.4.5 门控信号发生模块的设计与实现 9.4.6 频率计的Verilog-HDL描述 9.4.7 频率计的硬件实现 -based on V
leon3-clock-gate
- Clock gating logic for LEON3 processor.
NPL-all
- A Numerical Photonics library written in C++. The library includes beam propagation method, coupled mode method, Bragg Gating Analysis, transfer matrix method, and vectorial Fourier Decomposition method. Very useful in s
mpg_ss
- VOD实用工具,可以从MPG文件之中, 分离视频和音频, 视频直接压缩保存DIV5格式, 音频直接保存为WAV格式, 支持双音轨 必须预先安装DSHOW组件 (AX文件:REGSVR32 /C /S [FILENAME].AX) -VOD practical tool that can MPG document, separate video and audio, video compression preservation DIV5
時脈 Gating Clock
- Gating Clock
fpga时钟设计
- 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操 作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将 导致错误的行为，并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可 分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上 述四种时钟类型的任意组合。-without the expense of
9.4_PULSE_FRE
- 基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 9.4.1 脉冲频率的测量原理 9.4.2 频率计的工作原理 9.4.3 频率测量模块的设计与实现 9.4.4 while循环语句的使用方法 9.4.5 门控信号发生模块的设计与实现 9.4.6 频率计的Verilog-HDL描述 9.4.7 频率计的硬件实现 -based on V
leon3-clock-gate
- Clock gating logic for LEON3 processor.
NPL-all
- A Numerical Photonics library written in C++. The library includes beam propagation method, coupled mode method, Bragg Gating Analysis, transfer matrix method, and vectorial Fourier Decomposition method. Very useful in s
LCM_C51_indirect
- QingDa光电5.6吋彩色液晶屏的C51控制程序。 硬件采用的是寄存器选通的间接控制方式！-QingDa photoelectric screen 5.6-inch color LCD of the C51 control procedures. Hardware used is register indirect gating control mode!
Clock_Gating
- 本文重点详细讲述了gate clock的用法和设计-In this paper, the focus of a detailed account of the gate clock usage and design
AT89S51
- 用AT89S51单片机的P0.0/AD0－P0.7/AD7端口接数码管的a－h端，8位数码管的S1－S8通过74LS138译码器的Y0－Y7来控制选通每个数码管的位选端。AT89S51单片机的P1.0－P1.2控制74LS138的A，B，C端子。在8位数码管上从右向左循环显示“12345678”。能够比较平滑地看到拉幕的效果。-AT89S51 MCU with P0.0/AD0-P0.7/AD7 port access digital
Clockgatingandclockskewanalysis
- 门控时钟与时钟偏移分析,也是时钟的问题，集中先发一下-Clock gating and clock skew analysis, is also the issue of clock
segmentation
- This paper provides an algorithm for partitioning grayscale images into disjoint regions of coherent brightness and texture. Natural images contain both textured and untextured regions, so the cues of contour and tex
hundunjiami
- 混沌加密应用于实际电路的VHDL语言编写的电路选通程序。-Chaotic encryption used in the actual circuit of the circuit VHDL language gating process.
2
- FPGA设计中几个基本问题的分析及解决 多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of bur
power_gating
- ieee paper on power gating and can be use full for implementing on ip core
power_converter_craig_no_Trans
- This power converter in matlab with no transformer. The full control is using. PID controller for the gating signal of SCR. The phase angle has been controlled-This is power converter in matlab with no transformer. The f
CodeSLAM
- EKF-SLAM Simulator (version 2.0) --- --- --- This simulator demonstrates a simple implementation of standard EKF-SLAM. It permits simple configuration via configfile.m to perform SLAM with various control p