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Floating-point-complex-radix-2-decimation-in-time-
- 浮点复数基2时分FFT完成适当的FFT，输出改写输入缓冲器。-floating-point complex FFT-based two hours to complete the FFT output rewritten input buffer.
Fast Floating-Point Arithmetic Emulation on the Bl
- ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
Fast Floating-Point Arithmetic Emulation on the Bl
- ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
flowadd
- verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
51单片机汇编葵花宝典
- 各种51单片机源程序集，包括浮点数的计算，多字节的加减等算法的实现-SCM source scr ipts, including floating point calculations, multi-byte such as addition and subtraction algorithm implementation
vhdldesign
- 浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Floating-point-complex-radix-2-decimation-in-time-
- 浮点复数基2时分FFT完成适当的FFT，输出改写输入缓冲器。-floating-point complex FFT-based two hours to complete the FFT output rewritten input buffer.
fpu
- 利用FPGA实现浮点运算的verilog代码 希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
03_Quantization
- This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable
dsp-fixed-point-computation
- 该文档主要讲述dsp芯片中进行定点运算所设计的基本问题，分别介绍了定标、从浮点到定点的运算，定点的快速运算及其实现。文档中举出大量的例子说明，相信下载阅读后肯定会很有收获。-the document focuses on the dsp chip sentinel operation designed the basic problem introduced calibration, from floating-point to fix
ieee_matrix
- 用汇编写的矩阵乘法和IEEE浮点数转换 -was compiled using the matrix multiplication and IEEE floating point conversion
div2
- 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
ieee754c
- 浮点和16进制互相转换软件。用于单片机调试，浮点-定点转换，我在开发中经常用到。 很不错的软件。-Hexadecimal floating-point and 16 co-conversion software. For single-chip debug, floating-point- fixed-point conversion, I frequently used in the development. Very good
AccelDSP
- AccelDSP Synthesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs
fsqr
- 功能：浮点数开平方（快速逼近算法） 入口条件：操作数在[R0]中。 出口信息：OV=0时，平方根仍在[R0]中，OV=1时，负数开平方出错。 影响资源：PSW、A、B、R2～R7 堆栈需求： ２字节 -Features: Floating-point square root (fast approximation algorithm) entrance conditions: operand in [R0] in.
VHDLfolat
- 开发环境是FPGA开发工具，主要讲解用CPLD/FPGA实现浮点数的运算-Development environment is the FPGA development tools, primarily on the use of CPLD/FPGA to achieve floating-point arithmetic
floating-point-adder1
- 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined
floating-point-adder
- verilog implementation of the floating point adder
floating-point-multiplier
- verilog implementation of the floating point multiplier