一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据-A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data

基于matalab simulink中dspbuider实现am调制，将mdl文件转化为vhdl文件，在quartus2里面进行下载验证-Matalab simulink based on the realization of dspbuider modulation am to mdl file into vhdl file, download it in quartus2 authentication