搜索资源列表
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口,程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
ddr_sdram_controller_vhdl
- ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
DDR_SDRAM
- 该项对于设计DDSRAM有很大的帮助,希望可以对你有所帮助。
ddr_sdram
- ddr_sdram的控制程序,希望有用。
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口,程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
ddr_sdram_controller_vhdl
- ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
DDR_SDRAM
- 该项对于设计DDSRAM有很大的帮助,希望可以对你有所帮助。-For the design of the DDSRAM have great help, I hope you can help.
DDR_SDRAM
- 利用fpga读写ddr的源代码 实测可以使用-Ddr use FPGA to read and write the source code can use the measured
DDR_SDRAM
- DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
DDR_SDRAM
- DDR——SDRAM学习资料,DDR——SDRAM学习资料-DDR- SDRAM learning materials, DDR- SDRAM learning materials
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
DDR_SDRAM
- ddr sdram 的控制程序,lattice的,比较好用的,大家-ddr sdram control program, lattice, and relatively easy to use, and we look
DDR_SDRAM
- SDRAM控制器的相关源程序代码 有需要的同学可以下载-SDRAM controller source code related to students in need can be downloaded
DDR-SRAM
- 自己汇总的一些Verilog HDL语言编写的,关于DDR_SDRAM的程序-Verilog HDL DDR_SDRAM
ddr_sdram
- 对ddrsdram操作,用VHDL语言实现,read,write的接口电路控制-Erase operation to read and write on the ddrsdram
DDR_SDRAM
- DDR_SDRAM的fpga实现,内有编写文档及代码,适合FPGA进阶的同学参考学习-DDR_SDRAM fpga implementation, documentation and code written inside, suitable for those students to learn advanced FPGA
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd,reset.vhd,ddr_dcm.vhd,user_if.vhd,ddr_sdram.vhd,Mt46v16m16.vhd以及仿真TB文件;设计采用Virtex ii系列芯片,DDR_SDRAM型号为Mt46v16m16,可用于进行DDR控制的初步学习使用;通过细致了解并进行逻辑控制,可深入理解DDR芯片内部构造; 支持133MHz系统时钟频率,突发长度为2,可进行读、写、NOP、激活、
DDR_sdram
- 文件里有DDR3/DDR4 sram的verliog模型,而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)