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DesignofanMP3PortablePlayerUsingaCoolRunnerCPLD.ra
- 描述了用CoolRunner CPLD实现mp3 player的一种方法，值得学习
cpld
- 本文详细分析了COOLRUNNER系列CPLD的结构,特点及功能,使用VHDL语言实现数字逻辑,实现了水下冲击波记录仪电路的数字电路部分.
Interface 8051 to Coolrunner CPLD(Xilinx App)
- Interface 8051 to Coolrunner CPLD(Xilinx App)
Interface 8051 to Coolrunner CPLD(Xilinx App)
- Interface 8051 to Coolrunner CPLD(Xilinx App)
DesignofanMP3PortablePlayerUsingaCoolRunnerCPLD.ra
- 描述了用CoolRunner CPLD实现mp3 player的一种方法，值得学习-Describes the CoolRunner CPLD with mp3 player realize a method, it is worth learning
cpld
- 本文详细分析了COOLRUNNER系列CPLD的结构,特点及功能,使用VHDL语言实现数字逻辑,实现了水下冲击波记录仪电路的数字电路部分.-In this paper, a detailed analysis of the CoolRunner CPLD series structure, characteristics and functions, the use of VHDL language digital logic, the
APPILICATIONOFXILINXCPLD
- CPLD COOLRUNNER XILINX -CPLD COOLRUNNER XILINX
uc_interface
- This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, a
VariPOD_src_0.2
- GUI for Amontec Chameleon POD clone with Xilinx Coolrunner inside.
cpld_applications_handbook_I
- Xilinx handbook for CPLD applications, featuring CoolRunner-II and XC9500XL CPLDs - Part I
pBlazIDE36
- There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popul
NANDInterface
- Xinlix CoolRunner-II cpld实现的nand FLASH接口-Xinlix CoolRunner-II cpld implementation nand FLASH Interface
lunwen
- spi协议简介及简单的spi接口的描述和基于CoolRunner CPLD 的SPI设计结构-Introduction and simple protocol spi spi interface descr iption of the SPI CoolRunner CPLD-based design structure
I2C_control
- Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ************************************************************************************************
I2C_vhdl
- IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this sign
manchester_verilog
- This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
manchester_vhdl
- This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
spi_cpld_vhdl
- The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified
uart_verilog
- The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL
DDR-with-CoolRunner-II
- 详细讲解了CoolRunner II CPLD与DDR SDRAM的接口设计-Explained in detail about the design of the CoolRunner II CPLDs and DDR SDRAM interface