CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。

CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。 -CPU design controlunit source, which comes with timing simulation. Sequencing Logic generated through control_signals

its a simple control unit source code for a basic microprocessor.

Control Unit VHDL code. Xilinx Spartan 3E board