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clock_VHDL
- VHDL设计的数字时钟，有闹钟、整点报时等功能
clock_VHDl
- 一个初学者写的时钟程序，VHDL语言，MAXPLUS环境。
clock_VHDL
- VHDL设计的数字时钟，有闹钟、整点报时等功能-VHDL design of the digital clock has an alarm clock, the whole point timekeeping functions
clock_VHDl
- 一个初学者写的时钟程序，VHDL语言，MAXPLUS环境。-The clock to write a beginners program, VHDL language, MAXPLUS environment.
clock_VHDL
- 主要供学习FPGA的人员学习如何写VHDL程序之用，该程序实现了时钟的二分频等功能。-Primarily for learning FPGA-VHDL program to learn how to write use, the program achieved the second clock frequency and so on.
clock_vhdl
- 使用quartus ii开发的FPGA电子时钟的VHDL源代码，分模块写法，在1602液晶上显示，具有走时，调节时间功能-Using quartus ii the development of electronic clock FPGA VHDL source code, sub-module written in the 1602 LCD display, with travel time, settling time functio
digital-clock_VHDL
- 使用VHDL实现数字时钟，已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA