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DCT域隐藏
- 当要隐藏信息时,在MATLAB的命令窗内输入命令: hide = myhide(carry,signal,x,y)； carry 用你的原始载体文件名代替，signal 用你所要隐藏的文件名代替 carry 和 signal 都必须是 *.* 的形式（注意不能省略单引号） x,y 是选取隐藏信息的位置坐标，在（x,y）和（y,x）处 生成的伪装载体文件名为hide.bmp 注意myhide.m文件，载体文件，隐藏文件都要在当前目录(cu
ripple-lookahead-carryselect-adder
- Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple
cla_src
- carry lookahead adder verilog program
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead a
CSLA_32
- 32bit carry select adder
save_adder
- implement of carry save adder with verilog
lookahead
- implement of carry look ahead adder vith verilog
carrysel_adder_files
- This has code of carry select adder.. It is written in VHDL.. Hope its useful for beginners .. All the best-This has code of carry select adder.. It is written in VHDL.. Hope its useful for beginners .. All t
RippleCarryAdder
- Ripple Carry Adder in Vhdl
lab7
- 在這個實習當中，我們學習利 用 Hierarchical VHDL code 的方式，來 實現一 個n-bit 的ripple-carry adder，並學習使用package。-In this practice among the profit we can learn to use Hierarchical VHDL code the way to achieve an n-bit future of t
hcsa_adder_latest(2).tar
- Hierarchical Carry Save Algorithm. HCSA Generic ALU.
cla
- Carry Look ahead adder
Carrylookaheadadder
- carry look ahead adder implented in 3 models of vhdl-carry look ahead adder implented in 3 models of vhdl
FOURBITRIPPLECARRYADDER
- four bit ripple carry adder implented in 3 models of vhdl-four bit ripple carry adder implented in 3 models of vhdl
5PG
- Design of High-Performance Low-Power Carry Select Adder using Dual Transition Skewed Logic (DTSL)I
p4_adder.tar
- 用vhdl实现的P4加法器，包括主要元件rca加法器，carry select adder,pg模块，并提供了一个测试文件，用modelsim测试通过-P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test fil
adder_csa
- carry select adder in verilog
carry-ripple
- carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code
Optimized-design-of-BCD-adder-and-Carry
- Optimized design of BCD adder and Carry
carry select addr
- vhdl code for carry select adder