搜索资源列表
an_dcfifo_top_restored
- alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。
alteral_train
- alteral训练新人的程序代码~~学习使用-alteral train new code of learning ~ ~
an_dcfifo_top_restored
- alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
SOPC_pio_irq
- 本源码为基于Alteral FPGA SOPC系统的PIO中断例程。-The source Alteral FPGA SOPC based system PIO interrupt routines.
clock
- 数字时钟的verilog程序，在alteral ep2c5t144调试成功-Digital clock verilog program
fpga_usb_serial_20091006.tar
- 免费的usb2.0源码,支持Xilinx和Alteral的FPGA-USB2.0 free sources
lift
- 简单的电梯程序，可以实现电梯的正常运行功能。测试平台：Alteral公司FPGA-Simple lift procedure, can achieve the normal operation of the elevator function. Test Platform: Alteral company FPGA
usb2.0_fpga
- 免费的USB2.0源码(支持Xilinx和Alteral的FPGA),用vhdl语言实现。-Free USB2.0 source (supports Xilinx and Alteral the FPGA), using vhdl language.
OV7670initial
- ov7670硬件初始化代码，运行在alteral cyclone 2 fpga上-the hardware initializition of ov7670,running at cyclone 2 fpga platform
IP
- ALTERAL的stratix4的IP核的使用讲解PPT，便于理解Stratix的IP核调用-The IP core stratix4 ALTERAL the use to explain the PPT, to facilitate the understanding the Stratix of IP core call
5SGSD5H3F35C4
- ALTERAL的Stratix5GS系列芯片的电路图、管脚分配、性能手册，方便配置芯片和使用资源-The schematic of ALTERAL the series of Stratix5GS chip, pin allocation, performance manuals, convenient configuration chip and use of resources
Altera-SOC-FPGA
- 讲述了Alteral公司SoC FPGA的几个应用实例- U8BB2 u8FF0 u4E86Alteral u516C u53F8SoC FPGA u7684 u51E0 u4E2A u5E94 u7528 u5B9E u4F8B
AD_FPGA_DSP
- 使用FPGA（alteral 类型的飓风四代）控制ADS8364进行数据的采集。但是运行后，运行结果显示会有数据乱窜现象，希望不是程序的问题。(provide a program (writing with Verilog HDL language) to control ADS8364 with FPGA.)
C5G_LPDDR2_RTL_Test
- LPDDR2工程，alteral的c5芯片，板子上验证过，可以直接用。(LPDDR2 project, alteral's C5 chip, has been verified on board and can be directly used.)
C5G_SRAM_RTL_Test
- 官网c5板子的SRAM工程，可以直接一直使用。(The SRAM project of official website C5 board can be used directly)