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ahb_interface
- AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
masterdecoder
- AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
ahb_system_generator_latest.tar
- this project relates ahb
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB
MAC-IP
- 关于千兆以太网的硕士论文，一边的mac层，一边是ahb总线slave接口。写的非常好。-Master s thesis on Gigabit Ethernet, while the mac layer, one side is ahb bus slave interface. Write very well.
AHB--Master
- Advanced High speed bus protocol
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
ahb_master
- AHB总线接口描述，MASTER的接口描述，AMB总线协议(AHB bus interface descr iption, MASTER interface descr iption, AMB bus protocol)
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)