搜索资源列表
Verilog_add4
- add4 verilog code -add4 Verilog code
ADD4-5
- 此程序为dsp原码程序，经过上机调试完全通过．-procedure for dsp original code procedures, after the last plane entirely through debugging.
Verilog_add4
- add4 verilog code -add4 Verilog code
ADD4-5
- 此程序为dsp原码程序，经过上机调试完全通过．-procedure for dsp original code procedures, after the last plane entirely through debugging.
add4
- 一个四位加法器的VHDL语言实现，并通过编译测试-A four-adder realization of the VHDL language, and compile test
add4
- 一个用vhdl代码设计的简单的加法器程序-it is a code designed by vhdl ,and it is used for adder
add4
- VC数据库编程,分为初级篇、中级篇和高级篇共17部分，该部分是第17部分。-VC database programming, divided into primary articles, intermediate, and advanced articles of chapter 17 of part of Section 17 of the part.
add4
- 该程序实现了往数据库中添加数据行，平时学习时使用的，仅供参考-add sql
add4
- 四位加法器verilog源代码，经过modelsim仿真验证正确，用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
add4
- 加法器的verilog代码，描述一个四位的加法器，可移植性很强，适合很多场合。-The adder verilog code, describe a four of the adder, portability is very strong, suitable for many occasions.
ADD4
- Adder programs for vhdl development
add4
- 并行计算的4位累加器，a和b分别为4为数据，cin为进位三者相加结果为sout和cout-4-bit parallel computing accumulator, a and b are 4 for the data, cin is carry addition result of the three sout and cout
add4
- 方便扩展学习的四位全加器；用VHDL语言描述实现，是初学者一个不错的学习历程。。。完整可运行工程喔-4 bits adder
add
- The circuit 1 in is a 1-bit binary adder with 3 inputs (A, B and Carry-In) and 2 outputs (Sum and Carry-Out).The circuit 2 depends on circuit 1 which create a VHDL file ADD4 which is a 4-bit binary adder built using ADD1
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic m