这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.

加减计数器 library ieee use ieee. std_logic-_1164.all entity dec3_8 is port(a,b,c,s1,s2,s3: in std_logic y: out std_logic_vector(0 to 7)) end architecture b of dec3_8 is si