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PCI_target
- VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
pingpufx
- 本设计以凌阳16位单片机SPCE061A为核心控制器件，配合Xilinx Virtex-II FPGA及Xilinx公司提供的硬件DSP高级设计工具System Generator，制作完成本数字式外差频谱分析仪。前端利用高性能A/D对被测信号进行采集，利用FPGA高速、并行的处理特点，在FPGA内部完成数字混频，数字滤波等DSP算法。
vhdl0716
- ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。
KCPSM3
- This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devices by Picoblaze
PCI_target
- VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
generic_fifo
- 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
vhdl0716
- ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo,
KCPSM3
- This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devices by Picoblaze -This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4
XilinxisdisclosingthisSpecification
- Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FP
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Cl
Xilinx
- Xilinx可编程逻辑器件的高级应用与设计技巧 全面介绍Xilinx的CoolRunnerII Spartan-3 Virtex-II VirtexII pro等器件的结构特性，以及ISE6及其辅助设计工具。 -Xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction t
soc-OverviewProcessors.pdf
- 几款处理器相互比较，包括EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)-OVERVIEW-EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the cl
FPGA_DSP
- Virtex-II Pro _ Virtex-II Pro X 完整数据手册(包含全部4个模块)；XtremeDSP开发套件Pro用户指南；及如何利用ML300 Virtex-II Pro开发系统着手开始搭建系统。-Virtex-II Pro _ Virtex-II Pro X Full Data Sheet (includes all four modules) XtremeDSP Development Kit Pro User
Virtex_II_Pro_LINUX
- 在XILINX Virtex-II Pro Development Board开发板上移植LINUX系统-Porting MontaVista Linux to the XUP Virtex-II Pro Development Board
ddr_sdr_V1_1
- DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes -
VHDL_RAM
- Virtex II pro RAM memory
DesignandFPGAImplementationof
- In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passb
Xilinx_question
- ：ISE5.1i是Xilinx推出的具有ASIC-strength的设计工具，它充分发掘了VirtexⅡPro系列芯片的潜力；Virtex-II Pro 系列芯片的密度是从40,000门到8,000,000门。同4.1i相比，设计人员在编译时所花的时间得到了成倍提高（从100,000/min增加到200,000门/min）并且在器件速度上增加了40 。-: ISE5.1i is a Xilinx introduced a ASIC-st
xapp866
- 用于 Texas Instruments 模数转换器的 Virtex-4 和 Virtex-5 接口-Texas Instruments ADC for Virtex-4 and Virtex-5 Interface