搜索资源列表
filter-vhdl-code
- filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, inclu
FIR
- 此文件包括FIR滤波器的设计对EDA的介绍，以及用VHDL语言实现FIR滤波器的FPGA实现-This document includes the design of FIR filters on the EDA
New_HighSpeed_FIR_S_P
- 新型串并架构的高速FIR滤波器,对研究VHDL实现FIR的朋友有用处-New type of string and structure of high-speed FIR filters, the study of VHDL friends realize FIR has useful
fir
- 滤波器的vhdl实现 滤波器的vhdl实现-Filter VHDL VHDL realization of filters to achieve
fir
- 本设计用verilog代码实现FIR滤波器！-Verilog code of the design FIR filters to achieve!
DDC_CIC
- 用CIC 和 FIR Filters设计的数字下变频器，DSP Builder6.1版工程文件-Using CIC and FIR Filters Design of Digital Down Converter, DSP Builder6.1 version of project file
fir
- 只是一个8阶的fir滤波器，希望对大家有用-Only an 8-band fir filters, useful for all of us hope
fri
- 滤波器的设计的，用于FIR滤波器的设计和应用-The design of filters for the FIR filter design and application
filter_vhdl
- vhdl语言编写的fir和iir滤波器程序。在quartus上仿真通过。-vhdl language program fir and iir filters. Quartus adopted in the simulation.
MyFilter
- FPGA实现数字滤波器，用VHDL语言实现的直接1型FIR滤波器，具有较好的参考价值。-FPGA realization of digital filters using VHDL language to achieve the direct FIR filter type 1, has a good reference value.
VHDL_FIR_PRO_scr
- 可编程的FIR滤波器VHDL实现，只要输入FIR的阶数以及系数，就可在FPGA中实现FIR滤波器-Programmable FIR filter VHDL implementation, simply enter the order number as well as the FIR coefficients, we can implement FIR filters in FPGA
fir_sig
- 直接型FIR滤波器，VHDL语言，程序结构简单，-A direct-type FIR filters, VHDL language, program structure is simple,
fir_filter
- 实现滤波器的功能，有限冲激响应（FIR）数字滤波器和无限冲激响应（IIR）数字滤波器广泛应用于数字信号处理系统中。IIR数字滤波器方便简单，但它相位的非线性，要求采用全通网络进行相位校正，且稳定性难以保障。FIR滤波器具有很好的线性相位特性，使得它越来越受到广泛的重视。-Realize the filter function, finite impulse response (FIR) digital filters and infin
32fir
- 32阶滤波器分布式算法实现的主程序代码,用EP2c35f84c8寄存器速率可达243.55MHz-32-order FIR digital filters: 32 filters distributed algorithm order the main program code, register with EP2c35f84c8 rate up to 243.55MHz
fir
- FPGA实现的FIR滤波器，很好的参考资料！-FPGA implementation of FIR filters, a very good reference!
VHDL
- 这个是基于一下的要求设计的：1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。-This is based on what the requirements of the design: an input and output data width is 12, 2, the order of the four stages of linear phase FIR filters,
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
FIR
- FIR滤波器的仿真和实现。包括matlab的仿真文件和基于VHDL语言的硬件实现代码。算法包括串行和并行两种。-Simulation and implementation of FIR filters. Including matlab simulation files and hardware implementation based on VHDL code. Including both serial and parallel a
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR deci