搜索资源列表
RS232-for-vdhl
- RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
VDHLexample
- 一些很有用的VDHL程序设计例子，大家可下载参考一下-some very useful simulated program design examples, we can download reference
8051_ip_8bitcpucodes
- 用VDHL编的8051ip核，其为8位cpu代码，好东西，希望对大家有帮助！
vhdlcoder
- VDHL的简单DEMO演示，有利于初学者学习使用
a8215
- 通过用FPGA的 VDHL语言 来实现8251的异步功能
FPGA-based-DAC
- 用fpga实现的DA转换器，有说明和源码，VDHL文件。 A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The
RS232-for-vdhl
- RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
VHDL-Programming-by-Example
- VHDL Programming by Example（McGraw.Hill著 电子版）-VHDL Programming by Example (McGraw.Hill an electronic version )
VDHLexample
- 一些很有用的VDHL程序设计例子，大家可下载参考一下-some very useful simulated program design examples, we can download reference
8051_ip_8bitcpucodes
- 用VDHL编的8051ip核，其为8位cpu代码，好东西，希望对大家有帮助！-VDHL made by the 8051ip nuclear, its 8 cpu code, good things, hope all of you help!
vhdlcoder
- VDHL的简单DEMO演示，有利于初学者学习使用-VDHL simple demo DEMO will help beginners learn to use
a8215
- 通过用FPGA的 VDHL语言 来实现8251的异步功能 -Through the use of FPGA-VDHL language to realize the asynchronous function 8251
FPGA-based-DAC
- 用fpga实现的DA转换器，有说明和源码，VDHL文件。 A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The
VDHL
- 电梯的设计·用来控制6层的电梯设计原来·VHDL语言-Elevator designed to control the lift design 6 original VHDL language
VDHL
- Verilog的135个经典设计实例，直流电机控制，游戏机，三态总线，加法器，锁存器等-Verilog s 135 classic design example, DC motor control, video game consoles, three-state bus, adder, latches, etc.
cookbook.pdf
- 我學習VDHL的幫助手冊,英文版的,但是很實用-I am learning VDHL the help of manuals, in English, but very practical
vhdl.tar
- vdhl and matlab, i think it good for you
38.58
- 基于VDHL的38译码器的实现与58分频器的实现 FPGA主芯片：CycloneII EP2C35F672C6-Based on VDHL decoder 38 with the divider 58 to achieve the main FPGA chip: CycloneII EP2C35F672C6
counter
- 利用EDA工具MAX-PlusII的VDHL输入法，输入VHDL程序，实现2位计数器，在七段译码器上以十进制显示：0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器；建立相应仿真波形文件，并进行波形仿真；分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the rea
VDHL
- VHDL 详细教程。 内包含VHDL语法。 值得收藏学习！-VHDL detailed tutorial. Contains VHDL syntax. Collection worth learning!