搜索资源列表
Full_Adder
- 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
fpu_v18
- <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd
Test_Bench
- 8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言，开发环境：FPGA)
Test_Bench
- 波形发生器.经典双进程状态机.相应加法器的测试向量
Full_Adder
- 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
fpu_v18
- <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd
Test_Bench
- 8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言，开发环境：FPGA)-Eight test vectors (Test_Bench) and example of waveform generator (VHDL language, development environment: FPGA)
Test_Bench
- 波形发生器.经典双进程状态机.相应加法器的测试向量-Waveform generator. Classic dual-process state machine. Corresponding adder test bench
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
test_bench
- test bench for booth multiplier
test_bench
- Test benching in VHDL
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
FIFO_TD
- FIFO的VHDL测试程序,在Modelsim下完全可以运行-The test_bench of fifo
test_bench
- test bench for booth multiplier
Modelsim_and_Test_Bench
- 详细介绍了Modelsim软件的使用方法，图文并茂，以及介绍了Test_Bench的编写规则和方法。-Introduces the method of using Modelsim software, illustrations, and introduces the rules and methods of Test_Bench.
div10_test
- 10分频Verilog代码，以及test_bench仿真代码。-DIV10 Verilog
viterbi_imp_de_tb_test
- This a Viterbi Decoding Algorithm Trace Back algorithm. Very useful for decoding in communication channel. the Survivor path is taken to be four bits. We have taken 4 states here. The branch metrics are calculates accord
filtra-lowpass
- this a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR-this is a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR