搜索资源列表
Synopsys
- Synopsys 8051 IP core documentation.
Synopsys Timing Closure Flow
- Synopsys Timing Closure Flow
DW8051
- 大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
Synopsys
- Synopsys 8051 IP core documentation.
PCI_144
- -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144---- Synopsys VHDL Solution using Xilinx XC7000 Library
Altera的IP源码8237
- 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Lab11
- 32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
DesignCompilerFAQ
- synopsys DC FRQ 最流行的综合工具
RTL-Implementation-Guide
- 想做一个合格的ic工程师么？这个文档告诉你怎样写高质量的rtl代码。这是SYNOPSYS注册用户才可下载的文档-Want a qualified engineer ic it? This document tell you how to write high quality code rtl. This is the Synopsys registered users can download the document
cla_dc
- a demo scr ipt of "carry lookahead adder" for synopsys design compiler
brentkung_adder
- Synopsys的DesignWare库中采用的brentkung高速加法器Verilog源代码生成,附相关文档-Synopsys
vmm-1.0.1.tar
- VMM 文档加源码, synopsys公司很好的验证资料-VMM Document Canadian source, synopsys good company to verify the information
Synopsys_8051
- MCU_8051的Synopsys，到现在，我还没有用过-MCU_8051 of Synopsys, until now, I have not used
DW8051
- Synopsys 公司的DW8051源代码，用verilog编写的，代码很完整，可以仿真，对采用8051核做嵌入式的人很有帮助-Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
vcs_simulation_mannual(Edition2)
- VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.-VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. Th
DC-RM_B-2008.09
- synopsys dc_shell 用户手册-reference manual of synopsys dc_shell
2008.09-scripts_only
- synopsys icc 使用参考脚本-reference scr ipt of synopsys icc
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL codin
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051