搜索资源列表
OpenSPARC_DDR2_controller_RTL_Files
- 基于FPGA的DDR2控制程序，用verilog编写的。-FPGA-based DDR2 control procedures, prepared by using Verilog.
ccx
- ccx的verilog代码,opensparc 的源代码-verilog of ccx
OpenSPARCT1_Micro_Arch
- Sun Opensparc体系结构说明文档-Sun Opensparc architecture documentation
OpenSPARC.Internals.Book.pdf
- 开源可扩充处理器架构 OpenSPARC Internals Book-Open-source scalable processor architecture OpenSPARC Internals Book
OpenSPARC-XilinxCollaboration.ppt
- OPENSPARC Introduction
doc
- The design document for opensparc T1, it is very usefull for the VHDL learner
Synopsys_90nm_lib_course-OpenSPARC
- 开源可扩充处理器架构.源代码Synopsys_90nm_lib_course-OpenSPARC_labs_final_041509-Synopsys 90nm lib course-OpenSPARC labs final 041509
OpenSPARC_FPGA_Tutorial_16
- 开源可扩充处理器架构.源代码OpenSPARC_FPGA_Tutorial_16-OpenSPARC FPGA Tutorial 16
S1 CPU core
- S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the l