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ck1
- 用FPGA实现的数码管时钟，使用的是Nexys4开发板，所以使用了视觉暂留原理实现数码管的显示。-FPGA implementation with digital clock, using Nexys4 development board, so the use of the principle of persistence of vision to realize digital tube display.
Nexys4_ISE_Basic
- DIGILENT NEXYS4 ISE BASIC
IO
- 基于NEXYS4 和ISE14.7开发的并行IO接口设计，达到数码管滚动显示数字的功能-NEXYS4 and ISE14.7 developed parallel IO interface based, to the digital display digital scroll function
stopwatch
- VHDL秒表设计，硬件环境为NEXYS4开发板，有暂停功能，7段数码管显示。-VHDL stopwatch design, the hardware environment for the NEXYS4 development board, a pause function, 7 digital tube display.
CompuertAnd.tar
- And gate in Verilog for Nexys4
nexys4-ddr_sw_demo
- The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx
NEXYS4.UCF
- constraint for nexys4
Uart
- Uart接口通信 华中科技大学 微机原理实验(Uart interface communication, Huazhong University of Science and Technology ,microcomputer principle experiment)
38DEC
- 基于Nexys4开发板的3-8译码器的实现(Implementation of 3-8 decoder based on Nexys4 development board)
Nexys-4-OOB-2016.4-2
- 此文件为NEXYS4官方demo，供大家参考(NEXYS4 official demo)
nexys4vgamouseoverlay
- Demo code for mouse, nexys4 made by digilent