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n栏栅解密算法
- 此小程序为N栏栅解密算法的一种，对某一N值加密过的密文进行解密，此时只要确定N值即可解密。作者：万艳良 单位：武汉理工大学-the procedure is one of n bit palisade decrypt arithmetic,if decrypting the file which has been encrypted with N that one of the number,at this time ,if
add_full_n
- 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.
sub_full_n
- 该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.
MoShiPiPei
- 有一串10000位数的主串由1、2、3、4四位数随机获得，n位模式串是指有4的n次方个模式串，如2位模式串有：11、12、13、14、21、22、23、24、31、32、33、34、41、42、43、44等16个数组成。现在进行模式匹配，假设主串为：431324113122341324132等等，则第一次比较是43，第二次比较是31，第三次比较是13，依此类推，每比较一次则落得模式串中的一个，当所有模式串（有4的n次方个）都被找到时
n栏栅解密算法
- 此小程序为N栏栅解密算法的一种，对某一N值加密过的密文进行解密，此时只要确定N值即可解密。作者：万艳良 单位：武汉理工大学-the procedure is one of n bit palisade decrypt arithmetic,if decrypting the file which has been encrypted with N that one of the number,at this time ,if
adderN
- N位加法器源代码，通用的，通过xilinx验证，希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
Dan
- N皇后问题，采用随机法和回溯法实现求解N皇后问题-N Queen
fuperm
- 应用JBuilder环境开发，输入一个正整数n,输出1~n的组成的全排列-JBuilder application development environment, enter a positive integer n, output 1 ~ n the composition of the entire array
lab7
- 在這個實習當中，我們學習利 用 Hierarchical VHDL code 的方式，來 實現一 個n-bit 的ripple-carry adder，並學習使用package。-In this practice among the profit we can learn to use Hierarchical VHDL code the way to achieve an n-bit future of t
m-operand-n-bit-adder
- n bit m operand adder
Exhaustive-N-binary-system-number
- 列举N位二进制数，的分治递归算法，由C语言写成，附带运行，生成文件-Enumerate the N-bit binary number, divide and conquer recursive algorithm, written in C, with run to generate the file
n-bit
- n bit parity generator is a versatile program that adds parity bits for any length of data the user enters . It accurately adds parity bits on the MSB and solves the problem during any kind of digital communication proto
N---Bit-Full-SUBSTRUCTURE
- VHDL program for “N Bit Substructure” behavioral design in Xilinx integrated software environment
N-DtoA-VHDL-AMS
- 下面是一个混合信号的例子,是一个N位D/A转换器的VHDL-AMS描述-The following is an example of a mixed signal that is a N bit D/A converter described in VHDL-AMS
8-bit-Restoring-Divider
- Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register i
N-BitComparator
- N-Bit Comparator Between X and Y
N-BitParallelLoadShifRegister
- N Bit ParallelLoadShiftRegister
n-bit adder
- n-bit optimized adder using VHDL
穷举n位二进制数
- 输入一个小于20的正整数n，要求按从小到大的顺序输出所有的n位二进制数，每个数占一行。(Enter a positive integer that is less than 20, and you want to output all of the n-bit binary Numbers in the order of small to large, each of which is a row.)
N bit Multiplier in Verilog
- N bit multiplier block written in verilog HDL language