Implementation of a JK and D flip-flop

基于VHDL语言设计的边沿JK触发器，及相应的仿真波形-VHDL language design based on the edge of JK flip-flop, and the corresponding simulation waveforms

本工程为jk触发器的verilog语言程序工程，安全有效，可独立使用，可作为一个独立的模块。-This project is jk flip-flop verilog language program works, is safe and effective, can be used independently as a separate module.