搜索资源列表
startup
- Spartan-3E starter开发板入门例程的重新编译版本，本版本使用最新版ISE14.1重新编译。补充缺少的文件，实际测试通过。-Spartan-3E starter development board entry routine re-compiled version, this version use the latest version ISE14.1 recompile. Added missing files, thr
Verilog
- 实现对文本的检测，实现关键字的过滤，开发工具 ISE14.1以上
fpga_nes-master
- 这是一个完整的红白机nes游戏fpga实现，经测试可用，使用ise14.1以上版本的工程文件，开发板使用的是xilinx spartan6-This is a complete NES nes games fpga implementation, the test is available, use ise14.1 above version of the project file, the development board usin
fifo
- fifo源码以及测试文件基于ISE14.2-fifo source and test files based on ISE14.2
CMI
- CMI编码解码源代码以及测试文件 基于ISE14.2-CMI codec source code and test files based ISE14.2
wtut_ver
- stopwatch 源代码基于ISE14.2-stopwatch source code is based ISE14.2
HelloZynq
- 基于ZYNQ-7000开发板的helloword project，已经配置开发板信息，可运行在14.4ISE环境下。-Based on zynq-7000 helloworld project with essential configuration information，run in ISE14.4
AutoESL
- 基于ZYNQ-7000EPP开发板的AutoESL 工程，可直接运行在ISE14.4环境下。-Based ZYNQ-7000EPP development board AutoESL project can be run directly in ISE14.4 environment.
13.1-Custom-IPcore
- 基于zynq-7000开发板的自定义IPcore源程序及工程，可运行在ISE14.4环境下。-based on zynq-7000 board with IPcore sourc project and .bit file，run in ISE14.4
13.2-pwm_driver
- 基于ZYNQ-7000开发板的pwm驱动工程，包含源程序，可运行在ISE14.4下。-Based ZYNQ-7000 development board pwm drive engineering, including source code, can be run under the ISE14.4.
Regfile
- 利用Xilinx ISE14.3，用Verilog HDL 语言编写的计算器与寄存器堆程序，在Spartan Ⅲ板上调试通过。-Use Xilinx ISE14.3, using Verilog HDL language of computers and register file program, Spartan Ⅲ board through debugging.
lab5
- 用xilinx ISE14.3开发的单周期CPU系统，面向spartan Ⅲ板，仿真调试与实际测试均已通过。-Developed by xilinx ISE14.3 single-cycle CPU system, facing the spartan Ⅲ board simulation debugging and practical tests have passed.
LEDs
- ISE实现流水灯，并使用开关控制流水灯走动速度，对于硬IP核初学者很有帮助，代码绝对在ISE14.6上做过验证。-ISE achieve water lights, and use the switch to control light water walking speed, hard IP core for beginners, code validation is absolutely done on ISE14.6.
VGA_SW_Verilog
- VGA IP硬核设计，通过开关简单控制输出图像，在ISE14.6验证通过。-VGA IP hard-core design, the output image by a simple control switch, ISE14.6 validation.
counter_16
- 基于ISE14.7开发的模16的计数器，使用的FPGA开发板为Spartan 3E Start Kit-Based on the development of mold counter ISE14.7 16, FPGA development board used for the Spartan 3E Start Kit
counter
- 利用verilog编写的分频计数器，包括0.01s,1ms，1s三个计数器，可适用于ise14.7开发环境-Use verilog to write a crossover counter, including 0.01s, 1ms, 1s three counters, applicable to ise14.7 development environment
sencond_counter
- 在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
kc705-pcie-rdf0106-14.4-c
- 适合ise14.4软件使用的KC705套件的PCIE核使用教程，这是相关的代码，实现了PCIE的基本功能 -KC705 ise14.4 software suite for use of the PCIE nuclear tutorial, which is the relevant code, to achieve the basic functions of PCIE
sdram
- ISE14.4环境编程，XILINX spartan3E,SDRAM完整编程-xilinx sdram
fifo
- FIFO源码以及测试文件基于ISE14，Verilog语言编写，全部工程。-FIFO based on source code and test files ISE14, Verilog language, the whole works.