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GMII-matlab
- 一个GM(1,1)模型的程序,添加到matlab目录中即可直接调用.附有一个关于灰色模型的简述文档,可对GM(1,1)原理有一个初始的了解.
ETHERNET
- 具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述
mii接口
- 以太网知识MII接口：本文主要分析MII/RMII/SMII，以及GMII/RGMII/SGMII接口的信号定义，及相关知识，同时本文也对RJ-45接口进行了总结，分析了在10/100模式下和1000M模式下的设计方法。
GMII-matlab
- 一个GM(1,1)模型的程序,添加到matlab目录中即可直接调用.附有一个关于灰色模型的简述文档,可对GM(1,1)原理有一个初始的了解.-A GM (1,1) model of the process, added to the matlab directory can be called directly. Accompanied by a brief descr iption of the gray model on the d
ETHERNET
- 具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述-With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog descr iption
MII-RMII-SMII-GMII
- OSI结构层中的物理层介绍，这是一个对MII层的基本介绍。-Structural layer in the OSI physical layer, which is a basic introduction to the MII layer.
fiber_ctrl
- lattice Diamond平台的千兆以太网光纤接口与GMII接口的转换-lattice Diamond Platform of Gigabit Ethernet optical fiber interface and GMII interface conversion
ethernet_interface
- 介绍以太网的接口MII, R GMII, GMII基础知识。-The Ethernet interface MII, RMII, RGMII, GMII basics.
gmii_tx_mac
- 实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。-Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.
DE3_NET_150_GMII_NET0_9.1
- 千兆以太网,ALTERA公司D3板网络通信，实现PC机控制板子LED级数码管/LCD屏显示（GMII）- Gigabit Ethernet, ALTERA company D3 board network communications, PC control board level digital tube LED/LCD screen display (GMII)
DE3_NET_150_GMII_NET1
- 例程2：千兆以太网,ALTERA公司DE3板网络通信，实现PC机控制板子LED级数码管/LCD屏显示（GMII）-Gigabit Ethernet, ALTERA company D3 board network communications, PC control board level digital tube LED/LCD screen display (GMII)
ipg
- GMII based PHY IDs for Linux v2.13.6.
NET-a-UART
- AR8031千兆以太网应用电路,使用altium designer设计,已经在ARM11上经过验证,稳定工作在千兆,接口为GMII和RG45,可以作为千兆以太网参考设计电路 -AR8031 Gigabit Ethernet application circuit design using altium design has been validated on ARM11, steady work in Gigabit GMII i
cvmx-helper-rgmii
- Functions for RGMII GMII MII initialization, configuration, and monitoring.
udp
- 基 于 f p g a 的Marvell 88E1111 以 太 网 控 制 器 的 设 计，能发送接收，通过GMII接口实现TCP/UDP 传输-Base on fpga Marvell 88E1111 to mt net control device de
dwmac-socfpga
- Overwrite val to GMII if splitter core is enabled. The phymode here is the actual phy mode on phy hardware, but phy interface EMAC core is GMII. -Overwrite val to GMII if splitter core is enabled. The phymode here is t
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk
ethernet_test
- 基于FPGA的千兆以太网通讯，通讯方式采用GMII总线通信(Gigabit Ethernet communication based on FPGA, communication using GMII bus communication)
s3mii_io
- 实现s3mii接口转gmii接口，gmii接口转换s3mii接口功能(convert s3mii to gmii)
DBSTAR_RGMII
- Verilog实现的RGMII和GMII接口转接，适合适配不同PHY芯片接口使用(Verilog implementation of RGMII and GMII interface transfer)