搜索资源列表
vhdl-dds
- fpga 控制dds 程序。希望对各位有用
Project1-DDS
- 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
DDSforsinandcos
- 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
DDS
- 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
DDFS_PLL_10DA_with51
- FPGA下的DDS程序的编写,VHDL语言,-FPGA under DDS preparation procedures, VHDL language,
dds
- DDS正弦信号发生器 频率和相位连续可调。频率最大2M
dds
- 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
vhdl-dds
- fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
ddsyixiang
- dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
FPGA
- FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
dds
- fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
dds
- 如何利用FPGA产生DDS调频信号 很具体的-How to make use of DDS generated FM signal FPGA specific
DDS
- 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
prog_dds
- FPGA VHDL DDS程序，采用FPGA实现1hz到100khz可调的dds程序，频率调节步长是变化的。-FPGA VHDL DDS program, using FPGA to achieve 1hz to 100khz adjustable dds procedures, the frequency adjustment step size is changing.
DDS-FPGA
- 基于FPGA的DDS资料！个人搜集的 可直接编译-FPGA-based DDS information!
DDS-FM-FPGA
- DDS介绍,FM信号发生器的设计!基于DDS技术的FM信号发生器的设计及其FPGA实现-DDS introduced, FM Signal Generator! FM signal based on DDS technology and FPGA Implementation Generator
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
FPGA-VHDL-DDS
- 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table
FPGA-VHDL-DDS
- 这是基于FPGA的直接数字频率合成器的程序，是VHDL语言-This is based on FPGA for direct digital frequency synthesizer program that is VHDL language