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FIR5
- 系数对称的FIR滤波器设计 * *N=8,h(n)=h(N-1-n) * *y(n)=h0*[x(n)+x(n-7)]+h1*[x(n-1)+x(n-6)] * * +h2*[x(n-2)+x(n-5)]+h3*[x(n-3)+x(n-4)]
fir5
- 5阶fir滤波器，有详细的程序和附有文档，5阶fir滤波器，有详细的程序和附有文档
FIR5
- 系数对称的FIR滤波器设计 * *N=8,h(n)=h(N-1-n) * *y(n)=h0*[x(n)+x(n-7)]+h1*[x(n-1)+x(n-6)] * * +h2*[x(n-2)+x(n-5)]+h3*[x(n-3)+x(n-4)]-Symmetrical coefficient FIR filter design** N = 8, h (n) = h (N-1-n)** y (n) = h0* [x (
fir5
- 5阶fir滤波器，有详细的程序和附有文档，5阶fir滤波器，有详细的程序和附有文档
FIR5
- 5阶数字滤波器FIR5，包括了Textio模拟等完整设计，VHDL-5_level digital filler, including Textio simulation
FIR5
- FPGA基于FIR的滤波，EP2C8芯片 40Mhz的采样频率，50KHz的截止频率的低通滤波，自己调试可用-FPGA-based FIR filter, EP2C8 chip 40Mhz sampling frequency, 50KHz cutoff frequency of the low pass filter, own debugging available