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- 1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
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- 2路视频光端机的,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES